A Fan-in Bounded Low Delay Adder for Nanotechnology
نویسندگان
چکیده
Adder is an important functional unit of a computer. This paper provides design of a low delay threshold adder (LDTA) using fan-in bounded gates in nanotechnology. An n-bit LDTA with a fan-in bound of M + 1 has delay of O(log(N/M)) and hardware complexity of O(N log(N/M)). This design strategy allows a trade-off between the fan-in bound, delay and the complexity.
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تاریخ انتشار 2010